Tactile board schematic, done (almost)
Spent today finishing the schematic for the 32×16 tactile readout board — 512 taxels, one board per hand, forearm-mounted near the wrist. It’s the readout layer for the ORCA hand v2 Touch, based on Binghao Huang’s Columbia design but adapted off Arduino Nano onto a bare ATmega328P so it actually fits somewhere sensible.
Every part is now placed. What’s left is DRC and layout.
What went in
The architecture hasn’t changed since I last wrote about it: four SN74HC595 shift registers drive 32 columns out to a 32-pin FPC, a CD74HC4067 muxes 16 rows back into a single ADC pin through a 20k pulldown, and Velostat sandwiched between the two flex circuits is the sensor. The ATmega scans columns, reads rows, ships frames over UART.
Today was the unglamorous half — power, decoupling, programming access, and a lot of net housekeeping.
Power OR-ing. BAT54C common-cathode diode so the board runs off USB-C on the bench or the JST harness in the arm, whichever is present, with no backfeed either way. Costs ~0.35V, which puts the rail at about 4.65V. Still comfortably above the 4.5V floor for 16MHz, and since the Velostat divider is ratiometric against AVCC, rail sag cancels out of the reading anyway.
Decoupling pass. 0.1µF at every 595’s VCC pin, the mux, both ATmega VCC pins, AVCC and AREF. 10µF at power entry and a second 10µF that belongs physically in the middle of the shift register bank. When RCLK pulses, all 32 columns update simultaneously — that’s the biggest current transient on this board, and it lands on the same rail feeding the analog supply.
AVCC filter. Ferrite bead (Sunlord GZ2012D101TF, 100Ω @ 100MHz) in series between the 5V rail and AVCC, with its own 0.1µF on the analog side. The mux common node is high-impedance — 20k against Velostat in the kΩ–MΩ range — so digital hash on the supply lands straight in the ADC if you let it.
Programming access. Went with six SMD test points instead of a real ISP header: MISO, SCK, MOSI, RESET, 5V, GND. Copper only, nothing populated, excluded from the BOM. A blank ATmega has no bootloader, so USB can’t reach it the first time — the CP2102N only gives you a UART, and there’s nothing on the chip listening yet. ISP is silicon, not software, so it works on a virgin part. One-time operation to burn the bootloader and set the fuses (factory default is internal 8MHz with CKDIV8, so the crystal gets ignored until you fix the low fuse). After that everything goes over USB-C forever.
Six pads, ~24mm² of board. For two boards a pogo jig isn’t worth buying — I’ll tack wires on, flash, and desolder.
The one that nearly got me
I renamed a batch of nets from PIN_nn to real names and broke the shift register chain doing it.
Renamed the QH’ outputs, didn’t rename the matching SER inputs, and the numbering ran backwards on top of that. Result: SR_CHAIN_2 ended up with three pins on it — two shift register outputs shorted together. Both push-pull. Any time U3 and U4 disagreed, that’s a direct rail-to-rail short through both output stages. Part-killer, not a logic bug.
Meanwhile three other nets were sitting there orphaned at one pin each, doing nothing.
The schematic looked correct at every intermediate step. Nothing renders differently when a net has three pins instead of two. The only thing that catches it is the pin count.
New rule: rename both ends of a net in the same edit, then check that net’s pin count before touching the next one. Batch renaming and verifying afterward is exactly how this happened.
Related: I flagged the SRCLR# ties as possibly missing at one point based on a PDF text export, and they were fine — the export just dropped them. Text extraction from a schematic PDF is not a netlist. Trust the netlist.
Also learned the hard way
Capacitors go across a rail to ground. Ferrites and series resistors go in the rail. I managed to wire a cap in series (blocks DC entirely, chip gets no power) and then later wire the ferrite as a shunt to ground (does nothing). Both in the same afternoon. Writing it down so it sticks.
Next
- DRC, then verify netlist pin counts —
5Vshould read 25,SRCLK6,SER3,RESET4,AVCC3 - Confirm the two schematic pages resolve into single nets rather than splitting at the page boundary. That’s the failure mode that would silently disconnect the entire ATmega from everything it drives
- Layout. Targeting 35×25mm, 4-layer. The extra layers buy a dedicated ground plane, which matters more here than 5mm of board edge —
TACT_ADCneeds to be short, guarded, and nowhere near SRCLK - Price JLCPCB assembly against hand-building it. Leaning toward hand assembly with a stencil, but the CP2102N is QFN-28 with an exposed pad, and both FPC connectors are 0.5mm pitch. Ordering spare boards and spare parts either way